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vishay siliconix SI1410EDH document number: 71409 s10-0935-rev. b, 19-apr-10 www.vishay.com 1 n-channel 20 v (d-s) mosfet features ? halogen-free according to iec 61249-2-21 definition ? trenchfet ? power mosfets: 1.8 v rated ? esd protected: 2000 v ? thermally enhanced sc-70 package ? compliant to rohs directive 2002/95/ec applications ? load switching ? pa switch ? level switch product summary v ds (v) r ds(on) ( )i d (a) 20 0.070 at v gs = 4.5 v 3.7 0.080 at v gs = 2.5 v 3.4 0.100 at v gs = 1.8 v 3.0 orderin g information: SI1410EDH-t1-e3 (lead (p b )-free) SI1410EDH-t1-ge3 (lead (p b )-free and halogen-free) markin g code aa xx lot tracea b ility and date code part # code yy sot-363 sc-70 (6-leads) 6 4 1 2 3 5 top v ie w d d g d d s d s g 1 k notes: a. surface mounted on 1" x 1" fr4 board. absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol 5 s steady state unit drain-source voltage v ds 20 v gate-source voltage v gs 12 continuous drain current (t j = 150 c) a t a = 25 c i d 3.7 2.9 a t a = 85 c 2.6 2.0 pulsed drain current i dm 8 continuous diode current (diode conduction) a i s 1.4 0.9 maximum power dissipation a t a = 25 c p d 1.56 1.0 w t a = 85 c 0.81 0.52 operating junction and storage temperature range t j , t stg - 55 to 150 c thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient a t 5 s r thja 60 80 c/w steady state 100 125 maximum junction-to-foot (drain) steady state r thjf 34 45
www.vishay.com 2 document number: 71409 s10-0935-rev. b, 19-apr-10 vishay siliconix SI1410EDH notes: a. pulse test; pulse width 300 s, duty cycle 2 %. b. guaranteed by design, not s ubject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. typical characteristics 25 c, unless otherwise noted specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static gate threshold voltage v gs(th) v ds = v gs , i d = 250 a 0.45 v gate-body leakage i gss v ds = 0 v, v gs = 4.5 v 1 a v ds = 0 v, v gs = 12 v 10 ma zero gate voltage drain current i dss v ds = 16 v, v gs = 0 v 1 a v ds = 16 v, v gs = 0 v, t j = 85 c 5 on-state drain current a i d(on) v ds = 5 v, v gs = 4.5 v 4 a drain-source on-state resistance a r ds(on) v gs = 4.5 v, i d = 3.7 a 0.055 0.070 v gs = 2.5 v, i d = 3.4 a 0.065 0.080 v gs = 1.8 v, i d = 1.7 a 0.080 0.100 forward transconductance a g fs v ds = 10 v, i d = 3.7 a 10 s diode forward voltage a v sd i s = 1.4 a, v gs = 0 v 0.75 1.1 v dynamic b total gate charge q g v ds = 10 v, v gs = 4.5 v, i d = 3.7 a 5.6 8 nc gate-source charge q gs 0.75 gate-drain charge q gd 1.10 tu r n - o n d e l ay t i m e t d(on) v dd = 10 v, r l = 10 i d ? 1 a, v gen = 4.5 v, r g = 6 0.15 0.25 s rise time t r 0.4 0.6 turn-off delay time t d(off) 1.9 2.8 fall time t f 1.2 1.8 gate-current vs. gate-source voltage 0 2 4 6 8 10 0 3 6 9 12 15 1 8 v gs - gate-to-so u rce v oltage ( v ) i gss - gate c u rrent (ma) gate-current vs. gate-source voltage 0.01 100 10 000 0.1 1 10 1000 0 36 912 v gs - gate-to-so u rce v oltage ( v ) i gss - gate c u rrent ( a) t j = 150 c t j = 25 c
document number: 71409 s10-0935-rev. b, 19-apr-10 www.vishay.com 3 vishay siliconix SI1410EDH typical characteristics 25 c, unless otherwise noted output characteristics on-resistance vs. drain current gate charge 0 2 4 6 8 012345 1.5 v 1 v v gs = 5 v thr u 2 v v ds - drain-to-so u rce v oltage ( v ) i d - drain c u rrent (a) 0.00 0.03 0.06 0.09 0.12 0.15 0.0 1.5 3.0 4.5 6.0 7.5 v gs = 4.5 v v gs = 2.5 v v gs = 1. 8 v r ds(on) - on-resistance ( ) i d - drain c u rrent (a) 0 1 2 3 4 5 0.0 1.5 3.0 4.5 6.0 7.5 v ds = 10 v i d = 3.7 a v gs - gate-to-so u rce v oltage ( v ) q g - total gate charge (nc) transfer characteristics capacitance on-resistance vs. junction temperature 0 2 4 6 8 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 v gs - gate-to-so u rce v oltage ( v ) i d - drain c u rrent (a) 125 c 25 c t c = - 55 c 0 200 400 600 8 00 1000 04 8 12 16 20 c rss c oss c iss v ds - drain-to-so u rce v oltage ( v ) c - capacitance (pf) 0.6 0. 8 1.0 1.2 1.4 1.6 1. 8 - 50 - 25 0 25 50 75 100 125 150 v gs = 4.5 v i d = 3.7 a r ds(on) - on-resistance ( n ormalized) t j - j u nction temperat u re (c)
www.vishay.com 4 document number: 71409 s10-0935-rev. b, 19-apr-10 vishay siliconix SI1410EDH typical characteristics 25 c, unless otherwise noted source-drain diode forward voltage threshold voltage 1.2 1.5 0.1 1 10 0 0.3 0.6 0.9 v sd - so u rce-to-drain v oltage ( v ) i s - so u rce c u rrent (a) t j = 150 c t j = 25 c - 0.4 - 0.3 - 0.2 - 0.1 0.0 0.1 0.2 - 50 - 25 0 25 50 75 100 125 150 t j - j u nction temperat u re (c) v gs(th) - v ariance ( v ) i d = 250 a on-resistance vs. gate-to-source voltage single pulse power, junction-to-ambient 0.00 0.05 0.10 0.15 0.20 0.25 0123456 i d = 3.7 a v gs - gate-to-so u rce v oltage ( v ) r ds(on) - on-resistance ( ) 0 7 35 21 2 8 0 1 1 . 01 0.01 0.001 14 po w er ( w ) time (s) normalized thermal transient im pedance, junction-to-ambient 0 0 6 0 1 1 100 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 1. d u ty cycle, d = 2. per unit base = r thja = 100 c/ w 3. t jm - t a = p dm z thja (t) t 1 t 2 t 1 t 2 n otes: 4. s u rface mo u nted p dm 10 -4 10 -3 10 -2 10 -1 sq u are w a v e p u lse d u ration (s) n ormalized effecti v e transient thermal impedance
document number: 71409 s10-0935-rev. b, 19-apr-10 www.vishay.com 5 vishay siliconix SI1410EDH typical characteristics 25 c, unless otherwise noted vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?71409 . normalized thermal transient impedance, junction-to-foot 0 1 1 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 10 -4 10 -3 10 -2 10 -1 sq u are w a v e p u lse d u ration (s) n ormalized effecti v e transient thermal impedance
l c e e 1 e d e 1 a 2 a a 1 1 -a- b -b- 23 654 package information vishay siliconix document number: 71154 06-jul-01 www.vishay.com 1

dim min nom max min nom max a 0.90 ? 1.10 0.035 ? 0.043 a 1 ? ? 0.10 ? ? 0.004 a 2 0.80 ? 1.00 0.031 ? 0.039 b 0.15 ? 0.30 0.006 ? 0.012 c 0.10 ? 0.25 0.004 ? 0.010 d 1.80 2.00 2.20 0.071 0.079 0.087 e 1.80 2.10 2.40 0.071 0.083 0.094 e 1 1.15 1.25 1.35 0.045 0.049 0.053 e 0.65bsc 0.026bsc e 1 1.20 1.30 1.40 0.047 0.051 0.055 l 0.10 0.20 0.30 0.004 0.008 0.012 7 nom 7 nom ecn: s-03946?rev. b, 09-jul-01 dwg: 5550
an815 vishay siliconix document number: 71334 12-dec-03 www.vishay.com 1 single-channel little foot sc-70 6-pin mosfet copper leadframe version recommended pad pattern and thermal performance introduction the new single 6-pin sc-70 package with a copper leadframe enables improved on-resistance values and enhanced thermal performance as compared to the existing 3-pin and 6-pin packages with alloy 42 leadframes. these devices are intended for small to medium load applications where a miniaturized package is required. devices in this package come in a range of on-resistance values, in n-channel and p-channel versions. this technical note discusses pin-outs, package outlines, pad patterns, evaluation board layout, and thermal performance for the single-channel version. basic pad patterns see application note 826, recommended minimum pad patterns with outline drawing access for vishay siliconix mosfet s, ( http://www.vishay.com/doc?72286 ) for the basic pad layout and dimensions. these pad patterns are sufficient for the low to medium power applications for which this package is intended. increasing the drain pad pattern yields a reduction in thermal resistance and is a preferred footprint. the availability of four drain leads rather than the traditional single drain lead allows a better thermal path from the package to the pcb and external environment. pin-out figure 1 shows the pin-out description and pin 1 identification.the pin-out of this device allows the use of four pins as drain leads, which helps to reduce on-resistance and junction-to-ambient thermal resistance. figure 1. sot-363 sc-70 (6-leads) 6 4 1 2 3 5 top view d d g d d s for package dimensions see outline drawing sc-70 (6-leads) ( http://www.vishay.com/doc?71154 ) evaluation boards single sc70-6 the evaluation board (evb) measures 0.6 inches by 0.5 inches. the c opper pad traces are the same as in figure 2. the board allows examination from the outer pins to 6-pin dip connections, permitting test sockets to be used in evaluation testing. see figure 3. figure 2. sc-70 (6 leads) single 52 (mil) 96 (mil) 13 (mil) 71 (mil) 0, 0 (mil) 18 (mil) 16 (mil) 26 (mil) 26 (mil) 654 3 2 1 the thermal performance of the single 6-pin sc-70 has been measured on the evb, comparing both the copper and alloy 42 leadframes. this test was first conducted on the traditional alloy 42 leadframe and was then repeated using the 1-inch 2 pcb with dual-side copper coating.
an815 vishay siliconix www.vishay.com 2 document number: 71334 12-dec-03 figure 3. front of board sc70-6 back of board sc70-6 vishay.com thermal performance junction-to-foot thermal resistance (package performance) the junction to foot thermal resistance is a useful method of comparing different packages thermal performance. a helpful way of presenting the thermal performance of the 6-pin sc-70 copper leadframe device is to compare it to the traditional alloy 42 version. thermal performance for the 6-pin sc-70 measured as junction-to-foot thermal resistance, where the ?foot? is the drain lead of the device at the bottom where it meets the pcb. the junction-to-foot thermal resistance is typically 40 c/w in the copper leadframe and 163 c/w in the alloy 42 leadframe ? a four-fold improvement. this improved performance is obtained by the enhanced thermal conductivity of copper over alloy 42. power dissipation the typical r ja for the single 6-pin sc-70 with copper leadframe is 103 c/w steady-state, compared with 212 c/w for the alloy 42 version. the figures are based on the 1-inch 2 fr4 test board. the following example shows how the thermal resistance impacts power dissipation for the two different leadframes at varying ambient temperatures. alloy 42 leadframe room ambient 25 c elevated ambient 60 c p d t j(max) t a r ja p d 150 o c 25 o c 212 o c w p d 590 mw p d t j(max) t a r ja p d 150 o c 25 o c 212 o c w p d 425 mw cooper leadframe room ambient 25 c elevated ambient 60 c p d t j(max) t a r ja p d 150 o c 25 o c 124 o c w p d 1.01 w p d t j(max) t a r ja p d 150 o c 60 o c 124 o c w p d 726 mw as can be seen from the calculations above, the compact 6-pin sc-70 copper leadframe little foot power mosfet can handle up to 1 w under the stated conditions. testing to further aid comparison of copper and alloy 42 leadframes, figure 5 illustrates single-channel 6-pin sc-70 thermal performance on two dif ferent board sizes and two different pad patterns. the measured steady-state values of r ja for the two leadframes are as follows: little foot 6-pin sc-70 alloy 42 copper 1) minimum recommended pad pattern on the evb board v (see figure 3. 329.7 c/w 208.5 c/w 2) industry standard 1-inch 2 pcb with maximum copper both sides. 211.8 c/w 103.5 c/w the results indicate that designers can reduce thermal resistance (r ja ) by 36% simply by using the copper leadframe device rather than the alloy 42 version. in this example, a 121 c/w reduction was achieved without an increase in board area. if increasing in board size is feasible, a further 105 c/w reduction could be obtained by utilizing a 1-inch 2 square pcb area. the copper leadframe versions have the following suffix: single: si14xxedh dual: si19xxedh complementary: si15xxedh
an815 vishay siliconix document number: 71334 12-dec-03 www.vishay.com 3 time (secs) figure 4. leadframe comparison on evb thermal resistance (c/w) 0 1 400 80 160 100 1000 240 10 10 -1 10 -2 10 -3 10 -4 10 -5 alloy 42 320 time (secs) figure 5. leadframe comparison on alloy 42 1-inch 2 pcb thermal resistance (c/w) 0 1 250 50 100 100 1000 150 10 10 -1 10 -2 10 -3 10 -4 10 -5 200 copper copper alloy 42
application note 826 vishay siliconix www.vishay.com document number: 72602 18 revision: 21-jan-08 application note recommended minimum pads for sc-70: 6-lead 0.096 (2.438) recommended mi nimum pads dimensions in inches/(mm) 0.067 (1.702) 0.026 (0.648) 0.045 (1.143) 0.016 (0.406) 0.026 (0.648) 0.010 (0.241) return to index return to index
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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